The present invention relates to the field of programmable devices. Programmable devices, such as FPGAs, typically include thousands of programmable logic cells that use combinations of logic gates and/or look-up tables to perform logic operations. Programmable devices also include a number of functional blocks having specialized logic devices adapted to specific logic operations, such as adders, multiply and accumulate circuits, phase-locked loops, and one or more memory units for storage and retrieval of data used by the logic cells. The logic cells and functional blocks are interconnected with a configurable switching circuit. The configurable switching circuit selectively routes connections between the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function.
The configuration of the logic cells, functional blocks, switching circuits, and other components of the programmable device is referred to as configuration data. Users specify a user design that performs a desired information processing function. Compilation software tools analyze the user design and generate corresponding configuration data that implements the desired information processing function using a programmable device. The user-created configuration data can be temporarily or permanently loaded into one or more programmable devices to implement the user design. If the user design is changed, updated configuration data can be loaded into the programmable device to implement the changed user design.
In some applications, a copy of the configuration data for a programmable device is stored in non-volatile memory, such as ROM, flash memory, EEPROM, or any other type of memory capable of storing data following the removal of power. Upon powering-up or after a device reset, the programmable device loads configuration data from the non-volatile memory to implement the desired user design. The non-volatile memory can be external to the programmable device or integrated with the programmable device. In the latter case, non-volatile memory can be included on the same chip as the programmable device or on a separate chip integrated into the same chip package as the programmable device.
Following the activation or reset of a programmable device, the internal voltages within the programmable device and integrated non-volatile memory must reach nominal operating levels. Read failures can result from attempts to read configuration data from the non-volatile memory prior to it reaching nominal operating levels, which in turn can corrupt the configuration of the programmable device.
Power-on-reset circuits inhibit the operation of the programmable device and integrated non-volatile memory until internal voltages reach nominal operating levels. Often, the programmable device and integrated non-volatile memory can require different amounts of time and/or different voltage levels to operate properly. Furthermore, the programmable device and integrated non-volatile memory can require different trip points, which is the voltage at which the power-on-reset circuit must inhibit operation. In some applications, the internal voltage levels of the non-volatile memory may be inaccessible to power-on-reset circuits located within the programmable device, thus power-on-reset circuits must rely on a predetermined time delay following a reset of the programmable device to estimate when it is safe to begin reading from the integrated non-volatile memory.
It is therefore desirable for a system to include a power-on-reset circuit suitable for use with non-volatile memory associated with a programmable device in a wide variety of configurations. It is further desirable for the power-on-reset circuit to have relatively small trip point variation across a wide range of process, supply voltage, and temperature variations, as well as at different clock speeds of the programmable device. It is also desirable for the power-on-reset circuit to support long time delays with minimal area cost on a programmable device.